1. Field of the Invention
The present invention relates to a liquid crystal display device.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, much effort has been made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as substitutes for CRTs. Of these flat panel displays types, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and facing each other with a liquid crystal layer interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal layer. Alignment of the liquid crystal molecules in the liquid crystal layer changes in accordance with the intensity of the induced electric field into direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a circuit diagram illustrating an LCD device according to the related art.
As illustrated in FIG. 1, in the related art LCD device 10, a plurality of pixels “P” are arranged in a matrix form. The pixels “P” are connected to a plurality of gate and data lines “GL” and “DL.” In addition, in each pixel “P,” a thin film transistor (TFT) “T” connected to the corresponding gate and data lines “GL” and “DL,” and a liquid crystal capacitor “CLC” and a storage capacitor “CST” connected to the TFT “T” are arranged.
A gate electrode of the TFT “T” is connected to the gate line “GL,” and a source electrode of the TFT “T” is connected to the data line “DL.” A pixel electrode, a common electrode, and a liquid crystal layer between the pixel and common electrodes form the liquid crystal capacitor “CLC.” The pixel electrode is connected to a drain electrode of the TFT “T” and applied with a pixel voltage (Vp). The common electrode is applied with a common voltage (Vcom). The storage capacitor “CST” is connected in parallel with the liquid crystal capacitor “CLC.”
During one frame, the gate lines “GL” are sequentially scanned, and the scanned gate line “GL” is applied with an on gate voltage (Vg). Accordingly, the TFT “T” connected to the scanned gate line “GL” is turned on and a channel of the TFT “T” is open. When the channel is open, a data voltage (Vd) is applied to the data line “DL.” The data voltage (Vd) passes though the open channel, and thus, the pixel electrode is charged with the pixel voltage (Vp). Since the common electrode is applied with the common voltage (Vcom), a liquid crystal voltage, which is a voltage difference between the pixel voltage (Vp) and the common voltage (Vcom), is charged in the liquid crystal capacitor “CLC.” An electric field induced by the liquid crystal voltage changes the alignment of the liquid crystal molecules in the liquid crystal layer.
When the gate line “GL” is applied with an off gate voltage (Vg), the channel of the TFT “T” is close and the pixel voltage (Vp) is maintained. The storage capacitor “CST” prevents a drop of the pixel voltage (Vp).
All pixels of FIG. 1 have the same structure and, therefore, have the same electrical properties. Since all pixels have the same electrical properties, they can be operated in the same manner. Accordingly, all TFTs “T,” which are main elements in determining the electrical properties, have the same structures.
FIG. 2 is a plan view illustrating the TFT of FIG. 1.
As illustrated in FIG. 2, the related art TFT “T” includes a gate electrode 25, a semiconductor layer 40 on the gate electrode 25, and source/drain electrodes 35, 37 on the semiconductor layer 40 and apart from each other. The source electrode 35 is connected to the data line “DL.” The gate electrode 25 is a portion of the gate line “GL” corresponding to the semiconductor layer 40. Although not shown in FIG. 2, the drain electrode 37 is connected to the pixel electrode.
A ratio of a width “W” and a length “L” (W/L ratio) of a channel “CH” and a gate-drain parasitic capacitance (Cgd) between the gate electrode 25 and the drain electrode 37 are main aspects of the electrical properties of the TFT “T.” As explained above, the related art TFTs “T” have the same structures in all pixels (P of FIG. 1). Accordingly, the W/L ratios of the channel “CH” and the gate-drain parasitic capacitances (Cgd) are the same in all TFTs “T.” The W/L ratio influences an on current in the channel “CH,” which is proportional to the W/L ratio. The gate-drain parasitic capacitance (Cgd) is generated by an overlap of the gate electrode 25 and the drain electrode 37. The gate-drain parasitic capacitance (Cgd) causes the pixel voltage (Vp) to drop. A relation of the drop of the pixel voltage (ΔVp) with respect to the gate-drain parasitic capacitance (Cgd) is expressed by, ΔVp=Cgd/(Clc+Cst+Cgd)*ΔVg (Clc is a liquid crystal capacitance, Cst is a storage capacitance, and ΔVg is expressed by Vgh (high gate voltage)−Vgl (low gate voltage)). In other words, the pixel voltage drop (ΔVp) is proportional to the gate-drain parasitic capacitance (Cgd).
Since the W/L ratios and the gate-drain parasitic capacitances in all related art TFTs “T” are uniform, all related art TFTs “T” have the same electric properties. However, since the process deviation is generated during actual fabrication of the LCD device, non-uniformity of the electric properties occurs. For example, when fabricating the TFTs “T,” thickness deviation of a thin film of the TFT “T” between the TFTs “T” at different pixel positions is actually generated. Due to the process deviation, electrical property deviation is caused. Therefore, deviation in the pixel voltage drop (dΔVp) between the related art pixels is caused according to pixel positions.
In addition, the gate and data voltages (Vg and Vd) are transmitted from one end to the other end of the gate and data lines (GL and DL), respectively. Accordingly, voltages are sufficiently applied to pixels adjacent to the one ends of the lines, but are not sufficiently applied to pixels adjacent to the other ends due to resistance-capacitance (RC) delay of the lines. Therefore, the deviation in the pixel voltage drop (dΔVp) between the related art pixels is caused according to pixel positions.
FIG. 3 is a graph illustrating the distribution of pixel voltage drop quantities measured at various positions of the related art LCD device. First to fifth pixels “P1” to “P5” are pixels at first to fifth positions “LP1” to “LP5” of FIG. 1 along left to right sides of the LCD device. In other words, the first pixel “P1” is disposed adjacent to the one side of the gate line applied with the gate voltage (Vg), the fifth pixel “P5” is disposed adjacent to the other side of the gate line, and the third pixel “P3” is disposed adjacent at a center portion of the gate line. The second pixel “P2” is disposed between the first and third pixels “P1” and “P3,” and the fourth pixel “P4” is disposed between the fifth and third pixels “P5” and “P3.”
As illustrated in FIG. 3, the pixels “P1” to “P5” at different positions “LP1” to “LP5” have different pixel voltage drops (ΔVp), and thus, deviation in the pixel voltage drop (dΔVp) of the pixels “P1” to “P5” is generated. Accordingly, common voltages (Vcom) required to normally operate the pixels “P1” to “P5” also have a deviation. For example, the first pixel “P1,” which has a pixel voltage drop (ΔVp) greater than the other pixels “P2” to “P5,” requires a common voltage (Vcom) less than the other pixels “P2” to “P5.” In contrast, the fourth pixel “P4,” which has a pixel voltage drop (ΔVp) less than the other pixels “P1” to “P3” and “P5,” requires a common voltage (Vcom) greater than the other pixels “P1” to “P3” and “P5.” Therefore, according to the pixel positions, distribution of the common voltages (Vcom) required for normal pixel operation is non-uniform and inversely proportional to the distribution of the pixel voltage drop (ΔVp).
However, since the same common voltage is applied to the pixels “P1” to “P5,” most pixels are applied with a common voltage that is different from the common voltage needed for normal operation. Therefore, most pixels are operated improperly. As a result, flicker and afterimage are generated, thereby degrading image quality.